The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to an electrostatic discharge protection circuit allowing enough time to discharge an electrostatic signal, and a method thereof.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a prior art electrostatic discharge (ESD) protection circuit 10, which is utilized for protecting an integrated device 20 from being damaged by an electrostatic signal. The ESD protection circuit 10 comprises a low pass filter 11, which comprises a resistor R and a capacitor C; an inverter 12, which includes a PMOS transistor Mpa and an NMOS transistor Mna; and a discharging circuit 13, which comprises an NMOS transistor Mnb. The connection between the low pass filter 11, the inverter 12, and the discharging circuit 13 are shown in FIG. 1. Furthermore, a first pad 14 is coupled to a first terminal N1, and a second pad 15 is coupled to a second terminal N2.
Please refer to FIG. 2. FIG. 2 is a timing diagram illustrating the voltages Va, Vc, and Vd at respective terminals N1, N3, and N4 of the related art ESD protection circuit 10 shown in FIG. 1. Initially, the voltages Va, Vc, and Vd at terminals N1, N3, and N4 are set to zero respectively. In other words, the PMOS transistor Mpa, the NMOS transistor Mna, and the NMOS transistor Mnb are initially turned off. When the electrostatic signal, which is the voltage Va, is injected to the first pad 14 at time t1, which has a peak voltage of V1′, the PMOS transistor Mpa will suddenly be turned on at time t1 to discharge the voltage Va at the first pad 14. Therefore, the voltage Va will instantaneously decrease to a voltage V3′, as shown in FIG. 2. Furthermore, the voltage at the terminal N4 will also be charged instantaneously into a voltage V2′ at time t1. Therefore, the voltage V2′ will turn on the NMOS transistor Mnb for discharging the voltage Va. Meanwhile, the low pass filter 11 proceeds to perform low pass filtering upon the voltage Va to generate the voltage Vc. As shown in FIG. 2, the voltage Vc will increase gradually because of the low pass filtering characteristic of the resistor R and the capacitor C. After a time interval Δt′, the voltage Vc will reach a voltage V4′ and turn on the NMOS transistor Mna to discharge the voltage Vd of terminal N4. Then, the PMOS transistor Mpa and the NMOS transistor Mnb will be turned off. Please note that, in the time interval Δt′, the voltage Vc increases gradually and the voltage Vd of terminal N4 decreases gradually, i.e. the currents that are conducted by the NMOS transistor Mnb and the PMOS transistor Mpa decrease gradually, and the current that is conducted by the NMOS transistor Mna increases gradually. Therefore, the voltage Va at the terminal N1 may increase greatly after the NMOS transistor Mnb is turned off at time t2, as shown in FIG. 2. This means that the charge at the terminal N1 caused by the electrostatic signal cannot be totally discharged by the NMOS transistor Mnb within the time interval Δt′. According to related art, the increasing voltage at terminal N1 will affect the normal operation of the integrated device 20.